1. Field of the Invention
The present invention relates to the field of electronic data processing systems and in particular to such a system that includes a digital scientific processor and related program instructions that include a jump instruction.
2. Description of the Prior Art
In the prior art it is known to store instructions in the instruction buffer of an electronic data processing system. The instruction buffer is addressed to cause an instruction N to be provided therefrom, which instruction N is passed into an instruction register and then into a function register. From the function register instruction N issues corresponding control signals to the system. It is also known that successive instructions N, N+1, N+2, etc. are successively addressed and passed from the instruction buffer in a serial manner through the same logic path into the instruction register and thence into the function register to provide corresponding control signals to the system. It is also known that if the instruction N is a jump instruction, an instruction controller causes the jump target instruction of the instruction N to be loaded into a jump target instruction register, which jump target instruction register is in logic parallel with the next instruction register. A selector circuit, which is intermediate the next instruction register and jump target instruction register and the instruction controller, is enabled such that if the jump criteria are not met, the selector circuit couples the instruction N+1 to the function register while, alternatively, if the jump criteria are met the selector circuit couples the jump target instruction to the function register.
Because the parallel coupled next instruction register and jump target instruction register and the associated selector circuitry require a large amount of space, as by requiring additional printed circuit card assemblies, it is desirable to eliminate the jump target instruction register and the selector circuit. The present invention is directed toward a scheme for providing a serial instruction flow with reduced space requirements and with no loss in performance.